How Do You Know When Your Test is Broken? SVA PaperPresentation SNUG Austin – 2014
Migrating Verilog to UVM for FPGA Core Verification UVM Presentation DVCon – 2013
Conscious of Streams – Managing Parallel Stimulus UVM PaperPresentation DVCon – 2012
Stacking UVCs Methodology UVM PaperPresentation DVCon – 2012
Integrating DesignWare USB 3.0 Device Controller into UVM Testbench UVM PaperPresentation SNUG SV – 2012
UVM Workshop – Verifying Blocks to IP to SOCs to Systems UVM Presentation DAC 2011
UVM Scoreboard UVM PaperPresentation DVCon – 2011
Testbench Configuration Mantra O/VVM PaperPresentation DVCon – 2010
Creating Highly Reusable Stimulus OVM PaperPresentation DVCon – 2009
Building Reusable Verification Environments with OVM OVM Article EDA Tech – 2008
Increasing Verification Productivity with VMM Applications (RAL) VMM Presentation DVCon 2010
Creating Highly Reusable Stimulus VMM PaperPresentation DVCon – 2009
Generating VMM Compliant Verification Environments VMM Presentation Synopsys Interop – 2008
Automated Release Management…$Priceless Release Mgmt PaperPresentation DVCon 2010
Release Management – 5 Steps to Automate Release Mgmt PaperPresentation SNUG San Jose – 2010

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