Topic
|
Focus
|
Link
|
Venue
|
Paradigm Works® Scoreboard™ |
UVM |
App Note – Download |
Web |
How Do You Know When Your Test is Broken? |
SVA |
Paper – Presentation |
SNUG Austin – 2014 |
Migrating Verilog to UVM for FPGA Core Verification |
UVM |
Presentation |
DVCon – 2013 |
Conscious of Streams – Managing Parallel Stimulus |
UVM |
Paper – Presentation |
DVCon – 2012 |
Stacking UVCs Methodology |
UVM |
Paper – Presentation |
DVCon – 2012 |
Integrating DesignWare USB 3.0 Device Controller into UVM Testbench |
UVM |
Paper – Presentation |
SNUG SV – 2012 |
UVM Workshop – Verifying Blocks to IP to SOCs to Systems |
UVM |
Presentation |
DAC 2011 |
UVM Scoreboard |
UVM |
Paper – Presentation |
DVCon – 2011 |
Testbench Configuration Mantra |
O/VVM |
Paper – Presentation |
DVCon – 2010 |
Creating Highly Reusable Stimulus |
OVM |
Paper – Presentation |
DVCon – 2009 |
Building Reusable Verification Environments with OVM |
OVM |
Article |
EDA Tech – 2008 |
Increasing Verification Productivity with VMM Applications (RAL) |
VMM |
Presentation |
DVCon 2010 |
Creating Highly Reusable Stimulus |
VMM |
Paper – Presentation |
DVCon – 2009 |
Generating VMM Compliant Verification Environments |
VMM |
Presentation |
Synopsys Interop – 2008 |
Automated Release Management…$Priceless |
Release Mgmt |
Paper – Presentation |
DVCon 2010 |
Release Management – 5 Steps to Automate |
Release Mgmt |
Paper – Presentation |
SNUG San Jose – 2010 |