4 Half-Days (Webex) / September 03-06, 2024

9:00 am – 12:00 pm CST / 7:00 am – 10:00 am PST

70% Lecture, 30% Lab

Intermediate – Advanced Level (Verilog experience required)

Introduce engineers to world-class SystemVerilog language capabilities using award-winning materials developed by renowned Verilog and SystemVerilog Guru, Cliff Cummings.

This training course is mostly design related but includes verification topics required to take follow-on UVM training. The course includes 7 different Finite State Machine (FSM) design techniques and fundamental SystemVerilog Assertion (SVA) training, which should be used by all design and verification engineers.

(NOTE: This course is taught as 4 Half-Days)

Download the SystemVerilog 2-Day Course Syllabus for more details.

The course materials (including Lab Exercises) are provided digitally and run on a Windows 10 PC and higher (no Mac).

Cliff will be on the Webex call 1 hour before the lecture and for 1½ hours after the lecture each day to help with labs and answer questions.

U.S. Class Hours:

9:00 am – 12:00 pm CST

7:00 am – 10:00 am PST