2 Half-Days (Webex) / August 24-25, 2023

10:00 am – 1:00 pm EDT / 7:00 am – 10:00 am PDT

70% Lecture, 30% Lab

Expert Level

Very advanced design techniques from Cliff’s award-winning presentations on the efficient implementation of multi-clock CDC and FIFO designs. These materials are not specific to SystemVerilog but solutions are shown using SystemVerilog syntax (advanced techniques that all design engineers should know – the stuff you did not learn in college).

(NOTE: This course is taught as 2 Half-Days)

Download the CDC/FIFO 1-Day Course Syllabus for more details.

The course materials (including Lab Exercises) are provided digitally and run on a Windows 10 PC and higher (no Mac).

Cliff will be on the Webex call 1 hour before the lecture and for 1½ hours after the lecture each day to help with labs and answer questions.

U.S. Class Hours:

Class hours on the U.S. East Coast: 10:00 am – 1:00 pm EDT
Class hours on the U.S. West Coast: 7:00 am – 10:00 am PDT

World Class Hours:

Class hours in India: 7:30 pm – 10:30 am IST
Class hours in Central Europe: 4:00 pm – 7:00 pm CEST