6 Half-Days (Webex) / January 4-5, 8-11, 2024

10:00 am – 1:00 pm EDT / 7:00 am – 10:00 am PDT

70% Lecture, 30% Lab

Advanced Level

The #1 priority in this course is to have engineers complete and understand as many full UVM self-checking test benches as time permits.

To become proficient at UVM verification, engineers need to gain experience coding multiple full, self-checking UVM test benches. Engineers will use the Sunburst Design uvmtb_template files to rapidly develop 10 full, self-checking block-level UVM test benches, plus other labs. This UVM training is unique since it explains the powerful and simple uvm_resource_db API and why engineers have been using the wrong uvm_config_db API for more than 10 years.

As part of the course objective, training will make verification engineers knowledgeable, proficient, and productive at UVM verification, using training materials and UVM template files developed by renowned Verilog, SystemVerilog, and UVM Guru, Cliff Cummings.

(NOTE: This course is taught as 6 Half-Days)

Download the UVM 3-Day Course Syllabus for more details.

The course materials (including Lab Exercises) are provided digitally and run on a Windows 10 PC and higher (no Mac).

Cliff will be on the Webex call 1 hour before the lecture and for 1½ hours after the lecture each day to help with labs and answer questions.

U.S. Class Hours:

Class hours on the U.S. East Coast: 10:00 am – 1:00 pm EDT
Class hours on the U.S. West Coast: 7:00 am – 10:00 am PDT

World Class Hours:

Class hours in India: 7:30 pm – 10:30 am IST
Class hours in Central Europe: 4:00 pm – 7:00 pm CEST